2nd Year B.E. Electronics (VLSI Design & Technology) at R.M.K College of Engineering, Chennai.
Creator of Silis — an open-source EDA platform that lets students run the full RTL-to-GDS II chip design flow without expensive commercial tools.
I am a 2nd year B.E. Electronics Engineering student specialising in VLSI Design & Technology at R.M.K College of Engineering, Chennai. I explore the complete chip design pipeline — from writing synthesisable RTL in Verilog all the way to GDS II tapeout.
I built Silis — an open-source EDA platform so that every student can access the full RTL-to-GDS II flow without paying for expensive tools. Silis is now adopted across multiple engineering colleges. I prefer to keep learning, continue challenging myself, and build things that actually matter.
A complete RTL-to-GDS II EDA tool built from scratch for students. Licensed open-source, adopted across multiple engineering colleges.
RISC-V integer ISA processor in Verilog with full testbench. Complete RTL → GDS II tapeout inside Silis.
16-bit arithmetic & logic unit. Self-written testbench, complete RTL and GDS II layout via Silis.
Configurable baud-rate UART transceiver. Complete serial protocol verification and full GDS II tapeout via Silis.
4-bit ALU synthesised and deployed on FPGA using Xilinx Vivado. Validated via bitstream generation.
Open to VLSI internships, research collaborations, and fresher roles. Drop a message!
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